LPDDR/DDR
Overview
The M SQUARE LPDDR4X PHY is a transceiver physical layer IP interface solution for ASICs and SOCs. Compatible with the universal IP protocol DFI 5.0, it can operate at the data rate up to 4267Mbps with 16-bit data width per channel. As illustrated in Figure 1, the LPDDR4X PHY block diagram for system application includes data and address transmit path, receiver data path and PLL block, and more. With its hybrid analog/digital architecture, M SQUARE’s IP delivers low power consumption, a compact area, and robust performance, making it well-suited for LPDDR4X applications.
Highlights
| Compliant with DFI5.0 for PHY and control interface |
| Compatible LPDDR4x up to 4267Mbps |
| Flexible channel architecture |
| Support PHY independent training mode using an embedded processor |
| Support Dual Rank |
| DVFS supporting 4 trained frequencies |
| Support BIST and loopback mode |
| Support background tracking for PVT compensation |
Integrated low-jitter PLL and DLL |
Compliant with JEDEC standard JESD209-4C |
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